dc.contributor.authorFoong, Huey Chian
dc.contributor.authorTan, Meng Tong
dc.contributor.authorZheng, Yuanjin
dc.date.accessioned2013-11-15T06:39:42Z
dc.date.available2013-11-15T06:39:42Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationFoong, H.C., Tan M.T., & Zheng Y. (2012). High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters. Journal of Circuits, Systems and Computers, 21(07), 1250062-.en_US
dc.identifier.urihttp://hdl.handle.net/10220/17692
dc.description.abstractThis paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulation is realized using a cascade of a second-order high-pass filter and a fourth-order band-stop noise shaping filter. Chopper modulation is further employed to reduce the effect of 1/f noise. These have significantly increased the signal-to-noise+distortion ratio (SNDR) and lead to high linearity. The proposed ADC was designed and fabricated using CMOS 0.18 μm process. From measurement, the differential and integral nonlinearities of the ADC are determined to be ±0.5 LSB and ±0.65 LSB, respectively. The SNDR of the ADC is 49 dB up to 500 kHz, which gives an ENOB of 8 bits and quantization step of 2 mV. The ADC also features a low power consumption of 120 μA and a small IC area of 0.18 mm^2.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesJournal of circuits, systems and computersen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleHigh linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC convertersen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1142/S0218126612500624


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