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Title: Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
Authors: Tan, Yung Sern
Yeo, Kiat Seng
Boon, Chirn Chye
Do, Manh Anh
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2011
Source: Tan, Y. S., Yeo, K. S., Boon, C. C., & Do, M. A. (2011). Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit. 2011 IEEE International Conference of Electron Devices and Solid-State Circuits, pp.1-2.
Abstract: In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two different ppms in both different conditions; a smaller ppm for in-lock condition and a larger ppm for out-of-lock condition. This paper also provides a detailed analysis of the proposed lock detector at different conditions. The proposed lock detector is simulated in 0.18- um technology and it consumes 1.1-mW at a 1.8V supply voltage.
DOI: 10.1109/EDSSC.2011.6117638
Rights: © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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