An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices
Date of Issue2013
IEEE International Symposium on Low Power Electronics and Design (2013 : Beijing, China)
School of Electrical and Electronic Engineering
As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main memory storage but also computing capability. In this paper, the domain-wall nanowire is studied for a memory-based computing platform towards ultra-low-power big-data processing. One domain-wall nanowire based logic-in-memory architecture is proposed for big-data processing, where the domain-wall nanowire memory is deployed as main memory for data storage as well as XOR-logic for comparison and addition operations. The domain-wall nanowire based logic-in-memory circuits are evaluated by SPICE-level verifications. Further evaluated by applications of general-purpose SPEC2006 benchmark and also web-searching oriented Phoenix benchmark, the proposed computing platform can exhibit a significant power saving on both main memory and ALU under the similar performance when compared to CMOS based designs.
DRNTU::Engineering::Electrical and electronic engineering
© 2013 IEEE. This is the author created version of a work that has been peer reviewed and accepted for publication by IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2013, IEEE. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6629318&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D6629318.