A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS
Date of Issue
2013Conference Name
IEEE International Symposium on Circuits and Systems (2013 : Beijing, China)
School
School of Electrical and Electronic Engineering
Related Organization
Broadcom Corporations, Irvine, CA, USA
Electrical and Computer Engineering, University of Idaho, Moscow, ID, USA
Electrical and Computer Engineering, University of Idaho, Moscow, ID, USA
Version
Accepted version
Abstract
This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-interleaved sampling of the signal in each stage of the ADC. A novel multi-phase clock generator is introduced to generate ADC timing signals. A 5-bit, 1.25 GS/s DBP ADC is designed in 65nm CMOS process. Post-layout simulations confirm that the proposed ADC achieves a peak SNDR of 30.5dB while consuming 4.7mW from a single 1.2V power supply.
Subject
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Type
Conference Paper
Rights
© 2013 IEEE.
This is the author created version of a work that has been peer reviewed and accepted for publication by IEEE International Symposium on Circuits and Systems (ISCAS) 2013, IEEE . It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: http://dx.doi.org/10.1109/ISCAS.2013.6572267.
Collections
http://dx.doi.org/10.1109/ISCAS.2013.6572267
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