Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter
Date of Issue2013
Asia and South Pacific Design Automation Conference (18th : 2013 : Yokohama, Japan)
School of Electrical and Electronic Engineering
School of Microelectronics Shanghai Jiao Tong University
It is unknown to perform efficient PLL system-level verification with consideration of jitter induced by substrate or power-supply noise. With the consideration of nonlinear phase noise macromodel, this paper introduces a forward reachability analysis with stable backward correction for PLL system-level verification with jitter. By refining initial state of PLL through backward correction, one can perform an efficient PLL verification to automatically adjust the locking range with consideration of environmental noise induced jitter. Moreover, to overcome the unstable nature during backward correction, a stability calibration is introduced in this paper to limit error. To validate our method, the proposed approach is applied to verify a number of PLL designs including single- LC or coupled-LC oscillators described by system-level behavioral model with jitter. Experimental results show that our forward reachability analysis with backward correction can succeed in reaching the adjusted locking range by correcting initial states in presence of environmental noise induced jitter.
DRNTU::Engineering::Electrical and electronic engineering
© 2013 IEEE. This is the author created version of a work that has been peer reviewed and accepted for publication by 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [DOI:http://dx.doi.org/10.1109/ASPDAC.2013.6509691].