TROJANUS : An ultra-lightweight side-channel leakage generator for FPGAs
Date of Issue2013
International Conference on Field-Programmable Technology (2013 : Kyoto, Japan)
School of Physical and Mathematical Sciences
In this article we present a new side-channel building block for FPGAs, which, akin to the old Roman god of Janus, has two contradictory faces: as a watermarking tool, it allows to uniquely identify IP cores by adding a single slice to the design; as a Trojan Side-Channel (TSC) it can potentially leak an entire encryption key within only one trace and without the knowledge of either the plaintext or the ciphertext. We practically verify TROJANUS' feasibility by embedding it as a TSC into a lightweight FPGA implementation of PRESENT. Besides, we investigate the leakage behavior of FPGAs in more detail and present a new pre-processing technique, which can potentially increase the correlation coefficient of DPA attacks.
© 2013 IEEE. This is the author created version of a work that has been peer reviewed and accepted for publication by 2013 International Conference on Field-Programmable Technology (FPT), IEEE. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [DOI:http://dx.doi.org/10.1109/FPT.2013.6718347 ].