dc.contributor.authorDo, Anh Tuan
dc.contributor.authorYin, Chun
dc.contributor.authorVelayudhan, Kavitha
dc.contributor.authorLee, Zhao Chuan
dc.contributor.authorYeo, Kiat Seng
dc.contributor.authorKim, Tony Tae-Hyoung
dc.date.accessioned2014-09-10T01:12:54Z
dc.date.available2014-09-10T01:12:54Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.citationDo, A. T., Yin, C., Velayudhan, K., Lee, Z. C., Yeo, K. S., & Kim, T. T. H. (2014). 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. IEEE journal of solid-state circuits, 49(7), 1487-1498.en_US
dc.identifier.urihttp://hdl.handle.net/10220/20473
dc.description.abstractThis work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz.en_US
dc.format.extent32 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE journal of solid-state circuitsen_US
dc.rights© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/JSSC.2014.2316241].en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
dc.title0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation toleranceen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/JSSC.2014.2316241
dc.description.versionAccepted versionen_US


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