dc.contributor.authorSergeichik, Vladimir V.
dc.contributor.authorIvaniuk, Alexander A.
dc.contributor.authorChang, Chip-Hong
dc.date.accessioned2015-03-03T09:21:08Z
dc.date.available2015-03-03T09:21:08Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.citationSergeichik, V. V., Ivaniuk, A. A., & Chang, C.-H. (2014). Obfuscation and watermarking of FPGA designs based on constant value generators. 2014 14th International Symposium on Integrated Circuits (ISIC), 608-611.en_US
dc.identifier.urihttp://hdl.handle.net/10220/25168
dc.description.abstractObfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value but will not be minimized by the synthesizer. CVGs can be used to create new logic primitives, embed watermarks and introduce fictive interdependencies in the circuit. They help to hide actual design performance information by tricking the synthesizer tools to generate deceiving delay reports through the false paths.en_US
dc.format.extent4 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseries
dc.rights© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISICIR.2014.7029471].en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
dc.titleObfuscation and watermarking of FPGA designs based on constant value generatorsen_US
dc.typeConference Paper
dc.contributor.conferenceInternational Symposium on Integrated Circuits (ISIC) (14th : 2014)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/ISICIR.2014.7029471
dc.description.versionAccepted versionen_US
dc.identifier.rims183019


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