A 4 GHz 60 dB variable gain amplifier with tunable DC offset cancellation in 65 nm CMOS
Kumar, Thangarasu Bharatha
Yeo, Kiat Seng
Date of Issue2014
School of Electrical and Electronic Engineering
This letter presents a compact CMOS based variable gain amplifier with 60 dB gain control range and a feedback reconfigurable dc offset cancellation. The design is a four-stage fully differential cascaded amplifier implemented using a 65 nm CMOS process. The amplifier achieves a current controllable gain range from -39.4 dB to +20.2 dB, a voltage tunable lower cutoff frequency from dc to 200 kHz, a consistent 3 dB bandwidth better than 4 GHz, a maximum dc power consumption of 26 mW, a measured in-band group delay variation of 20 ps, and a noise figure from 10 to 27 dB. The proposed VGA design occupies a compact die area of only 75 μm × 80 μm (excluding pads for measurement).
DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio
IEEE microwave and wireless components letters
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