A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os
Manoj P. D, Sai
Date of Issue2014
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
School of Electrical and Electronic Engineering
One memory-logic-integration design platform is developed in this paper with thermal reliability analysis provided for 2.5D through-silicon-interposer (TSI) and 3D through-silicon-via (TSV) based integrations. Temperature-dependent delay and power models have been developed at microarchitecture level for 2.5D and 3D integrations of many-core microprocessors and main memory, respectively. Experiments are performed by general-purpose benchmarks from SPEC CPU2006 and also cloud-oriented benchmarks from Phoenix with the following observations. The memory-logic integration by 3D RC-interconnected TSV I/Os can result in thermal runaway failures due to strong electrical-thermal couplings. On the other hand, the one by 2.5D transmission-line-interconnected TSI I/Os has shown almost the same energy efficiency and better thermal resilience.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
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