An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators
Tan, Xiao Liang
Chan, Pak Kwong
Date of Issue2014
School of Electrical and Electronic Engineering
This paper presents an asynchronous sub-two-step circuit architecture to reduce the complexity and power consumption of internal analog-to-digital converter (quantizer) for Continuous-Time Sigma-Delta Modulator (CTSDM). By using the proposed new circuit topology, only 1/3 of comparators for a 5-bit quantizer design are needed when compared with the conventional flash based counterpart. The proposed quantizer has been implemented and fabricated in a UMC 65-nm CMOS process. The measured results have shown that the quantizer consumes 0.59 mW at an operating frequency of 250 MS/s in a 1.2 V supply and achieves 28.82 dB SNDR (4.5 ENOB) from the output spectrum.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
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