dc.contributor.authorCheah, Hui Yan
dc.contributor.authorFahmy, Suhaib A.
dc.contributor.authorKapre, Nachiket
dc.identifier.citationCheah, H. Y., Fahmy, S. A., & Kapre, N. (2014). Analysis and optimization of a deeply pipelined FPGA soft processor. 2014 International Conference on Field-Programmable Technology (FPT), 235-238.en_US
dc.description.abstractFPGA soft processors have been shown to achieve high frequency when designed around the specific capabilities of heterogenous resources on modern FPGAs. However, such performance comes at a cost of deep pipelines, which can result in a larger number of idle cycles when executing programs with long dependency chains in the instruction sequence. We perform a full design-space exploration of a DSP block based soft processor to examine the effect of pipeline depth on frequency, area, and program runtime, noting the significant number of NOPs required to resolve dependencies. We then explore the potential of a restricted data forwarding approach in improving runtime by significantly reducing NOP padding. The result is a processor that runs close to the fabric limit of 500MHz with a case for simple data forwarding.en_US
dc.rights© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPT.2014.7082783].en_US
dc.subjectComputer Science and Engineering
dc.titleAnalysis and optimization of a deeply pipelined FPGA soft processoren_US
dc.typeConference Paper
dc.contributor.conference2014 International Conference on Field-Programmable Technology (FPT)*
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.versionAccepted versionen_US

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