dc.contributor.authorKapre, Nachiket
dc.contributor.authorDeHon, Andre
dc.identifier.citationKapre, N., & DeHon, A. (2009). Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. 2009 International Conference on Field Programmable Logic and Applications.en_US
dc.description.abstractAutomated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3- 182times for a Xilinx Virtex5 LX 330T, 1.3-33times for an IBM Cell, and 3-131times for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160 implementation for a variety of single-precision device models.en_US
dc.rights© 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPL.2009.5272548].en_US
dc.subjectComputer Science and Engineering
dc.titlePerformance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processorsen_US
dc.typeConference Paper
dc.contributor.conference2009 International Conference on Field Programmable Logic and Applications (FPL)en_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.versionAccepted versionen_US

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