Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing
Gwee, Bah Hwee
Date of Issue2014-04-20
School of Electrical and Electronic Engineering
We propose an ultra-low power memory design method based on the ultra-low (∼ 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage V L (∼ 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/V DD ) 2 × 100 %) due to reduced voltage swing (from V DD = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a 256×64 bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.
Read-decoupled – SRAM – Ultra-low power – Dual-voltage
Circuits, Systems, and Signal Processing
© 2014 Springer Science+Business Media New York. This is the author created version of a work that has been peer reviewed and accepted for publication by Circuits, Systems, and Signal Processing, Springer. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1007/s00034-014-9791-8].