Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/82870
Title: A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
Authors: Zhou, Rong
Chong, Kwen-Siong
Lin, Tong
Gwee, Bah Hwee
Chang, Joseph Sylvester
Keywords: Critical path
Dual-rail
Dynamic voltage scaling
Fast transition
Fine-grained
Asynchronous
Timing-tolerant
Issue Date: 2015
Source: Zhou, R., Chong, K.-S., Lin, T., Gwee, B. H., & Chang, J. S. (2015). A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2589-2592.
Abstract: We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports fasttransition DVS within one-and-a-half clock duration per operation, and its operation remains error-free during that duration; we define such attribute as half-clock-tolerant. Third, it consists of a single power source (single-VDD) which supports three voltage scales (1.2V, 0.8V and 0.5V) for power/speed tradeoffs, and has standardized 1.2V output to seamlessly interface with other proposed/conventional pipelines. These attributes are achieved due to the embodiment of a DVS power unit, asynchronous building blocks to control/synchronize the operation, a dual-rail critical path to innately detect the completion of the operation, and level shifters to standardize the output voltage. We demonstrate our proposed pipeline by designing a multiplier embodied in a Fast Fourier Transform processor (@65nm CMOS). We show that the multiplier based on our proposed pipeline, on average, is 1.94× more power-efficient than that based on a conventional pipeline
URI: https://hdl.handle.net/10356/82870
http://hdl.handle.net/10220/40367
DOI: 10.1109/ISCAS.2015.7169215
Rights: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2015.7169215].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers
TL Conference Papers

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