Counteracting differential power analysis: Hiding encrypted data from circuit cells
Ne, Kyaw Zwa Lwin
Akbar, Ali H.
Chang, Joseph Sylvester
Date of Issue2015
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
School of Electrical and Electronic Engineering
We propose a balanced Pre-Charge Static Logic (PCSL) circuit style for asynchronous systems, and compare it against other reported circuit styles to counteract differential power analysis (DPA). Our study shows that all these circuit styles (including our balanced PCSL) dissipate different energy due to data-dependency, and hence balancing the energy of circuits embodying these circuit styles remains challenging. However, in view of low circuit overheads and asynchronous operations (with noise generation), our balanced PCSL is still competitive in terms of DPA-resistance, requiring 3.5x less power traces than its NULL convention logic counterpart.
solid state circuits
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