dc.contributor.authorHo, Weng-Geng
dc.contributor.authorNe, Kyaw Zwa Lwin
dc.contributor.authorPrashanth Srinivas, Nagarajan
dc.contributor.authorChong, Kwen-Siong
dc.contributor.authorKim, Tony Tae-Hyoung
dc.contributor.authorGwee, Bah Hwee
dc.date.accessioned2016-10-17T03:52:26Z
dc.date.available2016-10-17T03:52:26Z
dc.date.issued2016
dc.identifier.citationHo, W.-G., Ne, K. Z. L., Prashanth Srinivas, N., Chong, K.-S., Kim, T. T.-H., & Gwee, B. H. (2016). Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 698-701.en_US
dc.identifier.urihttp://hdl.handle.net/10220/41565
dc.description.abstractWe propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First, we adopt the transmission gates (as opposed the cross-couple inverters) in the slave circuitry, saving 4 transistors. Second, we eliminate a transistor which uses to reset the slave circuitry, hence saving 1 transistor. Third, we apply the global inverse transistors (as opposed to the local inverse transistors) in the read /write circuit for each SRAM cell, hence further reduce 2 more transistors. As a result, our proposed TNIHE SRAM cell @ 65nm CMOS features ~17% smaller layout area. We design a 1k-byte memory based on the proposed TNIHE SRAM cells. On the basis of simulations, we show that our 1k-byte SRAM memory features overall ~13% smaller area, and dissipates on average, ~30% lower stand-by power than the reported NIHE counterpart.en_US
dc.format.extent4 p.en_US
dc.language.isoenen_US
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2016.7527336].en_US
dc.subjecttransistorsen_US
dc.subjectSRAM cellsen_US
dc.titleArea-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAMen_US
dc.typeConference Paper
dc.contributor.conference2016 IEEE International Symposium on Circuits and Systems (ISCAS)en_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/ISCAS.2016.7527336
dc.description.versionAccepted versionen_US


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