dc.contributor.authorHo, Weng-Geng
dc.contributor.authorPammu, Ali Akbar
dc.contributor.authorLiu, Nan
dc.contributor.authorNe, Kyaw Zwa Lwin
dc.contributor.authorChong, Kwen-Siong
dc.contributor.authorGwee, Bah Hwee
dc.date.accessioned2017-03-13T08:26:48Z
dc.date.available2017-03-13T08:26:48Z
dc.date.issued2016
dc.identifier.citationHo, W.-G., Pammu, A. A., Liu, N., Ne, K. Z. L., Chong, K.-S., & Gwee, B. H. (2016). Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. 2016 International Symposium on Integrated Circuits (ISIC).en_US
dc.identifier.urihttp://hdl.handle.net/10220/42164
dc.description.abstractWe report a security analysis of the asynchronous-logic (async) quasi-delay-insensitive (QDI) Weak-Conditioned Half-Buffer (WCHB) cell approach against the side-channel differential power analysis (DPA) attack. When compared to the synchronous-logic (sync) standard cell approach, the WCHB cell approach is more power-balanced during the logic switching due to the unique features as follows. First, the WCHB cell approach embodies dual-rail data-encoding scheme, featuring more balanced power dissipation for different output transitions. Second, the WCHB cell approach embodies a power-constant input detector that validate the input-completeness, featuring more balanced power dissipation for different input combination. Based on 65nm CMOS process, the standard and WCHB cell approaches are simulated for 7 library cells, and compared in terms of the normalized energy deviation (NED) and normalized standard deviation (NSD). Nonetheless, the WCHB cell approach features 62% lower NED and 69% lower NSD than the standard cell approach.en_US
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en_US
dc.format.extent4 p.en_US
dc.language.isoenen_US
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISICIR.2016.7829712].en_US
dc.subjectAsynchronous logicen_US
dc.subjectComputer circuitsen_US
dc.titleSecurity analysis of asynchronous-logic QDI cell approach for differential power analysis attacken_US
dc.typeConference Paper
dc.contributor.conference2016 International Symposium on Integrated Circuits (ISIC)en_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/ISICIR.2016.7829712
dc.description.versionAccepted versionen_US


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