Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
Lee, Kwang Hong
Tan, Chuan Seng
Date of Issue2016
School of Electrical and Electronic Engineering
The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.
CMOS integrated circuits
Applied Physics Express
© 2016 The Japan Society of Applied Physics. This is the author created version of a work that has been peer reviewed and accepted for publication by Applied Physics Express, The Japan Society of Applied Physics. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.7567/APEX.9.086501].