Highly secured arithmetic hiding based S-Box on AES-128 implementation
Pammu, Ali Akbar
Date of Issue2016
2016 International Symposium on Integrated Circuits (ISIC)
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
We propose an arithmetic hiding technique on Advanced Encryption Standard (AES) algorithm implementation to highly secure the algorithm against Side-Channel Attack (SCA). The arithmetic operations run parallel with Substitution-Box (S-Box) operation of the AES to hide the correlated leakage power dissipation with processed data. There are two key features in our proposed hiding technique. First, the function of the arithmetic hiding is independent with S-Box operation and its power dissipation is dominant over the S-Box. Therefore, the dependency of the total power dissipation with processed data in the AES algorithm is relatively low. Second, the security level of proposed technique against SCA based on Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) attack are increased by 119× and 63× respectively, compared with unprotected S-Box. This is due to the leakage physical parameters (i.e. power dissipation and EM emanation) which is generated by the arithmetic operation hides the leakage parameters of the S-Box operation. Based on the measurement results on Sakura-X FPGA board, which performs AES-128 algorithm, our proposed technique dissipates 3.8mW and features 1.18× higher power dissipation than the unprotected S-Box implementation. However, our proposed arithmetic hiding technique is highly secured, as the result of CPA and CEMA attack require 38,000 power traces and 44,000 EM traces respectively to reveal the secret key. The required number of traces are significantly higher than the unprotected S-Box, which is only 319 power traces and 691 EM traces respectively to uncover the same secret key.
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