dc.contributor.authorNi, Leibin
dc.contributor.authorHuang, Hantao
dc.contributor.authorLiu, Zichuan
dc.contributor.authorJoshi, Rajiv V.
dc.contributor.authorYu, Hao
dc.date.accessioned2017-09-26T08:13:47Z
dc.date.available2017-09-26T08:13:47Z
dc.date.issued2017
dc.identifier.citationNi, L., Huang, H., Liu, Z., Joshi, R. V., & Yu, H. (2017). Distributed In-Memory Computing on Binary RRAM Crossbar. ACM Journal on Emerging Technologies in Computing Systems, 13(3), 36-.en_US
dc.identifier.issn1550-4832en_US
dc.identifier.urihttp://hdl.handle.net/10220/43796
dc.description.abstractThe recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM crossbar--based computing is mainly assumed as a multilevel analog computing, whose result is sensitive to process nonuniformity as well as additional overhead from AD-conversion and I/O. In this article, we explore the matrix-vector multiplication accelerator on a binary RRAM crossbar with adaptive 1-bit-comparator--based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with the according control protocol. Both memory array and logic accelerator are implemented on the binary RRAM crossbar, where the logic-memory pair can be distributed with the control bus protocol. Experimental results have shown that compared to the analog RRAM crossbar, the proposed binary RRAM crossbar can achieve significant area savings with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in neural network--based machine learning such that the overall training and testing time can be both reduced. In addition, large energy savings can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.en_US
dc.description.sponsorshipNRF (Natl Research Foundation, S’pore)en_US
dc.description.sponsorshipMOE (Min. of Education, S’pore)en_US
dc.format.extent18 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesACM Journal on Emerging Technologies in Computing Systemsen_US
dc.rights© 2017 Association for Computing Machinery (ACM). This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery (ACM). It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1145/2996192].en_US
dc.subjectRRAM crossbaren_US
dc.subjectHardware acceleratoren_US
dc.titleDistributed In-Memory Computing on Binary RRAM Crossbaren_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1145/2996192
dc.description.versionAccepted versionen_US


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