A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance
Kim, Tony Tae-Hyoung
Date of Issue2017
School of Electrical and Electronic Engineering
Dual-port SRAMs with two sets of address bus and data IOs are widely employed in various applications to increase throughput. Conventional 8T dual-port SRAM suffers reliability issue at low voltages due to common-row-access disturbance. Specifically, a row is simultaneously accessed by two operations, which can flip existing data and cause incorrect read output. Previous work can address this stability issue by assisting circuitry at cost of timing. This paper presents a low voltage 12T 2RW SRAM featuring parallel access with suppressed disturbance to ameliorate the problem without performance degradation. The proposed SRAM cell suppresses the disturbance by separating read path from internal nodes and minimizing the probability of the worst case stability with area penalty of 6%. In addition, hierarchical bitlines and a virtual ground technique are employed to further lower the minimum operating voltage and power consumption. A 16 kb SRAM has been fabricated in a 65 nm CMOS technology and extended the operating voltage from super-threshold region to 0.4 V at common-row-access scenario.
Static Random Access Memory (SRAM)
© 2017 Elsevier Ltd. This is the author created version of a work that has been peer reviewed and accepted for publication by Microelectronics Journal, Elsevier Ltd. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1016/j.mejo.2017.01.003].