dc.contributor.authorJayakrishnan, Mini
dc.contributor.authorChang, Alan
dc.contributor.authorKim, Tony Tae-Hyoung
dc.date.accessioned2018-07-27T03:54:56Z
dc.date.available2018-07-27T03:54:56Z
dc.date.issued2018
dc.identifier.citationJayakrishnan, M., Chang, A., & Kim, T. T.-H. (2018). Opportunistic design margining for area and power efficient processor pipelines in real time applications. Journal of Low Power Electronics and Applications, 8(2), 9-.en_US
dc.identifier.issn2079-9268en_US
dc.identifier.urihttp://hdl.handle.net/10220/45295
dc.description.abstractThe semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques.en_US
dc.format.extent18 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesJournal of Low Power Electronics and Applicationsen_US
dc.rights© 2018 The Author(s). Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).en_US
dc.subjectVariation Toleranceen_US
dc.subjectSlack Balancingen_US
dc.titleOpportunistic design margining for area and power efficient processor pipelines in real time applicationsen_US
dc.typeJournal Article
dc.contributor.researchVIRTUS, IC Design Centre of Excellenceen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.3390/jlpea8020009
dc.description.versionPublished versionen_US
dc.contributor.organizationVIRTUS, IC Design Centre of Excellenceen_US


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