dc.contributor.authorNg, K. A.
dc.contributor.authorChan, Pak Kwong
dc.date.accessioned2009-04-17T10:23:39Z
dc.date.available2009-04-17T10:23:39Z
dc.date.copyright2005en_US
dc.date.issued2005
dc.identifier.citationNg, K. A., & Chan, P. K., (2005). A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout. IEEE Transactions on Circuits and Systems, 52(10), 2065-2074.en_US
dc.identifier.issn0098-4094
dc.identifier.urihttp://hdl.handle.net/10220/4561
dc.description.abstractA new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1 noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with 4 TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8- m CMOS process. Index Terms—Crosstalk, equalizers, integrated circuit, layout, switched-capacitor (SC) circuit, time-multiplexed (TM) circuit.en_US
dc.format.extent10 p.
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE transactions on circuits and systemsen_US
dc.rightsIEEE Transactions on Circuits and Systems. © 2006 IEEE. Journal can be found at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=31.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
dc.titleA time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layouten_US
dc.typeJournal Article
dc.identifier.doihttp://dx.doi.org/10.1109/TCSI.2005.852921
dc.description.versionPublished versionen_US


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