Design of a low power wide-band high resolution programmable frequency divider
Yu, Xiao Peng
Do, Manh Anh
Yeo, Kiat Seng
Date of Issue2005
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 μm CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
IEEE transactions on very large scale integration (VLSI) systems
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