Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/89075
Title: In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies
Authors: Liang, Zhipeng
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2018
Source: Liang, Z. (2018). In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal–oxide–semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise. High in-band phase noise leads to serious consequences in communications, such as degraded signal-to-noise ratio (SNR) and constellation diagram, resulting in low communication quality. Therefore, low PLL in-band phase noise is crucial to the overall transceiver performance, especially in future high-speed high-quality wireless communications. Unfortunately, frequency synthesizers based on conventional PLL structures are facing challenges because their in-band phase noise is often limited by the phase detectors and charge pumps. Noises from these components are amplified due to the structure of the conventional PLLs. Furthermore, PLL often needs to achieve short settling time for some communication standards, and has to provide multi-phase output in some transceiver architectures. Inspired by these requirements, this thesis aims to enhance PLL in-band phase noise performance while meeting other important requirements of future wireless communications in the multi-GHz band. As the background of this research, conceptual PLL fundamentals related to phase noise will be briefly discussed. According to these fundamentals, the in-band phase noise is usually limited by the phase detector and charge pump in analog PLLs, and by the time-to-digital converter (TDC) in digital PLLs. Therefore, the objective of this research is specifically to reduce the adverse impact from these components. When choosing an analog or a digital PLL structure, characteristics of the adopted fabrication technology have to be considered. As the CMOS technology development is facing physical and economic limitations, two promising future CMOS technologies have been predicted, i.e., the more-than-Moore technology and the more-Moore technology. In regard to PLL implementation, the more-than-Moore technology permits the use of CMOS with larger feature size so that high-performance analog PLLs can be designed with mature methods, while the more-Moore technology keeps using the finer processes in which digital PLLs may be more suitable due to their promising performance with technology scaling. Both PLL types will be important in future advanced CMOS technologies. Therefore, this research investigates in-band phase noise reduction techniques for both analog and digital PLLs. Firstly, in-band phase noise reduction technique for analog PLLs is investigated. With mature design and verification methods, analog PLLs have evolved and achieved low power consumption in the past years. However, conventional analog PLLs suffer from the high in-band noise from the phase detector and charge pump because noises from these components are amplified. To reduce such adverse impact, one of the most attractive structures is the fractional-N subsampling phase-locked loop (SSPLL) that can remove this amplification. It has enabled promising in-band performance and fine tuning steps for wireless systems. However, prior arts of fractional-N SSPLLs need long time for calibrations (~20 ms), which is much longer than PLL settling time (normally less than 200 μs). So these prior arts are not suitable for wireless communications requiring short settling time, such as Bluetooth. To extend the SSPLL applications, we explore the fractional-N SSPLL with a calibration-free manner and propose a phase-switching subsampling (PS-SS) technique. Fabricated in a 65 nm CMOS technology, a 2.6-3.4 GHz fractional-N 8-phase SSPLL prototype using the proposed technique totally eliminates the need for calibration and achieves a low in-band phase noise of -100.3 dBc/Hz at 100 kHz offset. Under calibration-less measurement condition, this prototype achieves the best jitter performance and figure of merit (FoM) among fractional-N SSPLLs. By using the proposed PS-SS technique, a low in-band phase noise in future analog PLLs can be expected without the need for long calibration time. Secondly, in-band phase noise reduction technique for digital PLLs is investigated. For CMOS processes with small feature size, digital PLL has been proposed as a promising substitution of analog PLL due to many aspects. In these processes, in contrast to relying on the degraded transistor analog characteristics, digital PLLs take advantages of the improved digital characteristics and time resolution. Therefore, performance of digital PLLs can be improved with technology scaling. In addition, digital PLLs can also benefit from the automated digital design tools with shorter design cycle. However, in-band noise performance of digital PLLs is generally limited by the TDC noise. Among various TDC types, TDCs based on controlled oscillators have been reported to achieve low noise, hence low PLL in-band noise. Nevertheless, there is still a lot of headroom in such TDCs towards even lower noise. Besides, the operations of these TDCs draw different supply current at different time, leading to disturbance to power supply and to other circuitries when applied in a digital PLL. This can also affect the phase noise of the digital PLL. In this thesis, we investigate the controlled oscillator-based TDC family and propose an inverted ring oscillator (IRO) technique to further reduce TDC noise. A noise model is also proposed for noise prediction and design optimization for the controlled oscillator-based TDC family. An IRO-TDC prototype achieves an integrated noise of 196 fsrms in a 3 MHz bandwidth at 200 MS/s rate, showing lower in-band noise compared with state-of-the-art works. Moreover, a unique coherent phase noise cancellation (up to 36.4 dB cancellation ratio measured) and a constant TDC power dissipation were demonstrated, which can reduce the digital PLL in-band noise caused by coherent noises. In summary, this thesis proposes techniques and methods to improve PLL in-band phase noise in advanced CMOS technologies. The proposed techniques, models, and methods can be extended to more complicated designs in future researches and products.
URI: https://hdl.handle.net/10356/89075
http://hdl.handle.net/10220/46111
DOI: 10.32657/10220/46111
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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