Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/89232
Title: Designs and implementations of ultra-low power, low voltage digital signal processors
Authors: Ngoc, Le Ba
Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Integrated circuits
Issue Date: 4-Oct-2018
Source: Ngoc, L. B. (2018). Designs and implementations of ultra-low power, low voltage digital signal processors. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Conventional Fast Fourier Transform (FFT) using Radix-22 brought a significant improvement in FFT implementations to reduce circuit complexity and computational power. One of the most well-known architectures for VLSI implementation in Radix-22 is Single-path Delay Feedback (SDF) which has simple architecture and requires the smallest amount of memory. However, low throughput due to the single data line is its major drawback. In the first part of this thesis, Radix-22 Multiple-path Delay Commutator (MDC) architecture is proposed to achieve higher throughput while preserving low memory and hardware usage to reduce energy per conversion. In addition, a new input scheduling algorithm, parallel-pipelined architecture together with ultra-low power circuit design techniques are employed to increase the speed and minimize the total power consumption. A 1024-point high speed, ultra-low power Fast Fourier Transform (FFT) was fabricated using STM 65nm technology. The chip consumes 77.2 nJ/FFT with clock frequency of 400 MHz at 0.6V supply and it is able to operate at up to 600MHz at VDD=1V yielding 1.2 Gsample/s. Compared with the existing FFT research works, our proposed FFT processor achieved 8% lower than the lowest reported energy per FFT conversion in high performance domain (Msample and Gsample/s) while occupies only 42% of its area. In addition to the FFT processor, an ultra-low power hand gesture recognition processor is designed and implemented to further elaborate power saving techniques for system-on-chip implementations. In the past, many hand gesture recognition systems have been invented both for research interest and market demand. These systems require a great amount of power because of using active devices such as active IR sensor, RF sensor or Ultrasonic sensor which are not suitable for low power and portable applications. In our research, passive infrared (PIR) sensor is proposed to avoid high power demand. New algorithms for gesture recognition including sweeping, zooming and wake-up gesture detection is also presented and verified with real-time input from a customized analog front end as well as recorded input from a Heiman sensor. To further reduce power consumption, the algorithm is able to put the system into standby mode which operates at lower frequencies. Upon sensing a wake-up gesture, its active mode will be triggered to recover full operations. The completed hand gesture recognition SoC which includes an analog front end to process readings from IR sensor array together with two digital signal processors was fabricated in TSMC 65nm. The whole chip occupies an area of 8.1 mm2 in which the 16×4 input array DSP takes 580×300 µm and the 16×16 input version uses 580×580 µm. Test chips demonstrate successfully gesture detections for 8 sweeping directions, zooming action and a wake-up gesture. In active mode, the total power consumption of the SoC is 260 µW and it is 46 µW in idle mode. The DSP consumes 28.6 µW for detecting 16×4 input and 66.8 µW for 16×16 input. Power and area specifications of the proposed SoC are suitable for mobile and smart device applications. To our best knowledge, this work marks the first SOC hand gesture recognition processor which is 6.6 times smaller area and 64 times higher resolution in comparison with the state-of-art passive IR sensor from Pyreos.
URI: https://hdl.handle.net/10356/89232
http://hdl.handle.net/10220/46221
DOI: https://doi.org/10.32657/10220/46221
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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