A pole sharing technique for linear phase switched-capacitor filter banks
Chang, Joseph Sylvester
Tong, Yit Chow
Date of Issue1990
School of Electrical and Electronic Engineering
A switched-capacitor pole sharing technique for implementing bandpass filter banks is proposed. Using this technique, hardware reduction is achieved in two ways. First, the efficient nonminimum phase Lerner filter approximation is employed to minimize the number of poles required to satisfy a given filter specification in frequency and time domains; this approximation is more efficient than the common minimum phase filter approximations used in many reported filter bank designs. Second, the number of poles is reduced by pole sharing where an n-pole pair per channel bandpass filter bank is realized with only (n - 2) additional pole pairs per channel after the first channel, hence a saving of two pole pairs per channel. In the case of a four-pole pair (eighth order) per channel 25 channel filter bank example discussed in this paper, the number of poles saved is nearly 50%. The proposed hardware reduction methodology is micropower compatible, and is achieved without placing extra demands on the speed of operational amplifiers employed and without resorting to complicated clocking strategies; only a biphasic clock is used. Phase reversal for vocoder applications is easily achieved without incurring any additional hardware or compromising desirable features of the filter bank realization. Single parameter and statistical multiparameter sensitivity analyses are derived. The multiparameter sensitivity for the filter realized as a summation (parallel) of biquadratic sections is compared against the cascade structure. A uniformly and nonuniformly spaced filter bank were simulated with SWITCAP and part of the uniformly spaced filter bank was constructed on a breadboard. The near linear phase in the passband and sharp attenuation in the stopband responses obtained agreed with filter specifications.
DRNTU::Engineering::Electrical and electronic engineering
IEEE transactions on circuits and systems
© 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.