Analysis and design of power efficient class D amplifier output stages
Chang, Joseph Sylvester
Tan, Meng Tong
Tong, Yit Chow
Date of Issue2000
School of Electrical and Electronic Engineering
A Class D amplifier comprises a pulse width modulator and an output stage. In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts.We compare the relative merits of these layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): 1) optimization to a single modulation index point and 2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype IC’s.
DRNTU::Engineering::Electrical and electronic engineering
IEEE transactions on circuits and system-I : fundamental theory and applications
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