Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/88586
Title: Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders
Authors: Balasubramanian, Parvathavarthini
Yamashita, Shigeru
Keywords: DRNTU::Engineering::Computer science and engineering
Asynchronous Design
Full Adder
Issue Date: 2016
Source: Balasubramanian, P., & Yamashita, S. (2016). Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. SpringerPlus, 5, 440-. doi:10.1186/s40064-016-2074-z
Series/Report no.: SpringerPlus
Abstract: This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.
URI: https://hdl.handle.net/10356/88586
http://hdl.handle.net/10220/46942
ISSN: 2193-1801
DOI: 10.1186/s40064-016-2074-z
Rights: © 2016 Balasubramanian and Yamashita. This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.