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|Title:||Analysis and design of switching amplifiers for smartphones||Authors:||He, Huiqiao||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||31-Dec-2018||Source:||He, H. (2018). Analysis and design of switching amplifiers for smartphones. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||This thesis pertains to the analysis and design of switching amplifiers with improved specifications over the state-of-the-art for smartphones, including higher power-efficiency to address the short battery lifespan, lower noise, and wider bandwidth. The specific switching amplifiers are the Class D amplifier (CDA) for audio applications and the hybrid CDA for supply modulators for envelope tracking (ET) radio frequency (RF) power amplifiers (PAs). For the audio CDA, we investigate and analytically derive the effects of the non-ideal AC ground and mechanisms leading to their ensuing effects. Unlike the simplified single-ended integrator model used in literature, our analysis is based on a realistic fully-differential integrator model, and the open-loop and single-feedback topology in literature is extended to the ubiquitous double-feedback topology. We show that a reduction of the noise on the AC ground, as expected, would drastically improve the PSRR. However, the CDA with 1st-order integrators unexpectedly provides similar or higher PSRR than the CDA with 2nd-order integrators if both CDAs are designed with the same carrier attenuation. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs. For the hybrid CDA serving as the supply modulator for ET PAs, we investigate the power mechanisms thereto and propose two architectures – the first with the objective of reducing the power dissipation and extending the bandwidth of the supply modulator for a wideband ET PA for 40MHz LTE-A protocol, and the second with the objective of optimizing the power-efficiency of the supply modulator for multi-standard RF communication protocols, e.g., WCDMA, LTE, LTE-A, etc. To the best of our knowledge, this is the first supply modulator that is optimized for multi-standard RF protocols. The proposed two architectures were designed, monolithically realized and the functionality of the proposed architectures is verified experimentally. Specifically, for the former, our investigations include the analysis of the effect of the propagation delay to the hysteresis current of the hybrid CDA. On the basis of the said investigations, we propose a hybrid CDA with a delay-based hysteresis controller and Class AB amplifier. The proposed supply modulator (from measurements on the prototype IC) features the widest bandwidth (40MHz) amongst reported supply modulators to date, yet with highly competitive (other) parameters. Specifically, on the basis of a composite figure-of-merit (bandwidth x output power x power-efficiency x output swing x 1/ripple noise), our proposed supply modulator features a very significant 20x improvement over reported supply modulators. For the latter, we explore the design challenges of the hybrid CDA for multi-standard RF protocols and analyze the optimum switching frequency for maximum power-efficiency. We propose a hybrid CDA with a novel dual-mode Sigma-Delta control and adaptive biasing Class AB amplifier to self-adjust the operation according to the input envelope signals – the first-ever reported in literature for a hybrid CDA that is optimized for multi-standard communications protocols. On the basis of measurements on IC prototypes, our proposed supply modulator significantly improves its static power-efficiency by up to ~6%. When tracking 40MHz LTE-A envelope signals, the proposed supply modulator features the highest power-efficiency (85% at 1.8W) over the state-of-the-art and remains highly power-efficient (>80%) over a wide range of output power.||URI:||https://hdl.handle.net/10356/103340
|Appears in Collections:||EEE Theses|
checked on Dec 25, 2019
checked on Dec 25, 2019
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