dc.contributor.authorLiang, Zhipeng
dc.contributor.authorYi, Xiang
dc.contributor.authorYang, Kaituo
dc.contributor.authorBoon, Chirn Chye
dc.date.accessioned2019-05-22T08:56:38Z
dc.date.available2019-05-22T08:56:38Z
dc.date.issued2018
dc.identifier.citationLiang, Z., Yi, X., Yang, K., & Boon, C. C. (2018). A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique. IEEE Microwave and Wireless Components Letters, 28(2), 147-149. doi:10.1109/LMWC.2017.2779889en_US
dc.identifier.issn1531-1309en_US
dc.identifier.urihttp://hdl.handle.net/10220/48325
dc.description.abstractSub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful calibrations with extra silicon area and adjusting time (20 ms measured) to achieve low phase noise. For scenarios requiring short settling time such as frequency modulation, such a time consuming calibration is undesirable. This letter presents a phase-switching technique for fractional-N mode SSPLL to eliminate this calibration. The principle of the technique is analyzed and a prototype is fabricated in 65-nm CMOS technology. Even without calibration, the frequency synthesizer achieves a figure of merit of -234.3 dB under fractional-N operation, with 13.3-mW power consumption at 1.2-V supply.en_US
dc.description.sponsorshipMOE (Min. of Education, S’pore)en_US
dc.format.extent3 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE Microwave and Wireless Components Lettersen_US
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/LMWC.2017.2779889en_US
dc.subjectCalibration Freeen_US
dc.subjectCMOS Phase-Locked Loopen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleA 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling techniqueen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/LMWC.2017.2779889
dc.description.versionAccepted versionen_US


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