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|Title:||Implementation of an autonomous star recognition algorithm using hardware-software co-processing approach||Authors:||Dang, Le Dang Khoa||Keywords:||DRNTU::Science::Mathematics::Discrete mathematics::Algorithms
DRNTU::Engineering::Computer science and engineering::Computing methodologies::Pattern recognition
|Issue Date:||2019||Source:||Dang, L. D. K. (2019). Implementation of an autonomous star recognition algorithm using hardware-software co-processing approach. Master's thesis, Nanyang Technological University, Singapore.||Abstract:||There are various types of Attitude Determination sensors such as sun sensors, magnetometer, RF beacon but only Star Trackers can achieve the accuracy to arc seconds. A Star Tracker is an embedded system mounted on a spacecraft comprised of an Image sensor and a Computer. It helps determine the attitude of the satellite based on an Autonomous Star Recognition Algorithm. The Star Sensor would take an image of stars at its current position, and then the star pattern recognition algorithms would extract features to construct a pattern from the images. This pattern then is compared with a prebuilt Star Pattern Database to return the Star Identity of a star in the Image. This star identity is an important part to determine the attitude of the satellite. To implement the Algorithm on a specific hardware, the computing system must be appropriately chosen. Programmable System-on-chip is a technology that replaces the traditional ASIC by an FPGA combined with an Embedded Processor, integrated memories, a variety of peripherals to form an embedded computing system. The Programmable Logic is ideal for implementing high-speed logic, arithmetic and accelerating subsystems while the Processing System supports software routines and Operating systems. Based on this property, an algorithm can be partitioned into submodules to be co-processed by the hardware-software combination. The goal of this research is to partition and profile a Star Recognition Algorithm then implement these modules on both the Processing System and the Programmable Logics to analyze the Algorithm implementation regarding Performance, Area of Implementation, Power Consumption.||URI:||https://hdl.handle.net/10356/89067
|DOI:||10.32657/10220/48371||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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