Please use this identifier to cite or link to this item:
|Title:||Rapid memory-aware selection of hardware accelerators in programmable SoC design||Authors:||Prakash, Alok
Clarke, Christopher T.
DRNTU::Engineering::Computer science and engineering
|Issue Date:||2017||Source:||Prakash, A., Clarke, C. T., Lam, S.-K., & Srikanthan, T. (2018). Rapid memory-aware selection of hardware accelerators in programmable SoC design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 445-456. doi:10.1109/TVLSI.2017.2769125||Series/Report no.:||IEEE Transactions on Very Large Scale Integration (VLSI) Systems||Abstract:||Programmable Systems-on-Chips (SoCs) are expected to incorporate a larger number of application-specific hardware accelerators with tightly integrated memories in order to meet stringent performance-power requirements of embedded systems. As data sharing between the accelerator memories and the processor is inevitable, it is of paramount importance that the selection of application segments for hardware acceleration must be undertaken such that the communication overhead of data transfers do not impede the advantages of the accelerators. In this paper, we propose a novel memory-aware selection algorithm that is based on an iterative approach to rapidly recommend a set of hardware accelerators that will provide high performance gain under varying area constraint. In order to significantly reduce the algorithm runtime while still guaranteeing near-optimal solutions, we propose a heuristic to estimate the penalties incurred when the processor accesses the accelerator memories. In each iteration of the proposed algorithm, a two-pass method is employed where a set of good hardware accelerator candidates is selected using a greedy approach in the first pass, and a “sliding window” approach is used in the second pass to refine the solution. The two-pass method is iteratively performed on a bounded set of candidate hardware accelerators to limit the search space and to avoid local maxima. In order to validate the benefits of the proposed selection algorithm, an exhaustive search algorithm is also developed. Experimental results using the popular CHStone benchmark suite show that the performance achieved by the accelerators recommended by the proposed algorithm closely matches the performance of the exhaustive algorithm, with close to 99% accuracy, while being orders of magnitude faster.||URI:||https://hdl.handle.net/10356/99051
|ISSN:||1063-8210||DOI:||http://dx.doi.org/10.1109/TVLSI.2017.2769125||Rights:||© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2017.2769125||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Journal Articles|
Files in This Item:
|Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.pdf||1.79 MB||Adobe PDF|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.