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|Title:||Design, fabrication, and characterization of three-dimensional embedded capacitor in through-silicon via||Authors:||Lin, Ye||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging||Issue Date:||7-Jun-2019||Source:||Lin, Y. (2019). Design, fabrication, and characterization of three-dimensional embedded capacitor in through-silicon via. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||In this thesis, a novel integrated capacitor, called “three-dimensional (3-D) embedded capacitor” is proposed, designed, fabricated, and characterized for application in integrated circuits (ICs) with through-silicon vias (TSVs). A significant capacitance density enhancement can be achieved for this 3-D embedded capacitor, because it leverages on the existing TSVs. Compared to conventional trench capacitor, this technology does not consume much additional silicon area because it is embedded in the trenches of TSVs, instead of in the dedicated trenches. Firstly, two types of 3-D embedded capacitors are designed with different electrode deposition methods. The atomic layer deposition (ALD) type 3-D embedded capacitor features an extremely high capacitance density for high-end applications, whereas the sputtering type 3-D embedded capacitor features a higher electrode deposition rate and ease of integration for low-cost applications. Secondly, an electrical model of the 3-D embedded capacitor is constructed with analytical equations to predict its capacitance based on the physical design parameters. An ultra-high capacitance density, 5,621.8 nF/mm2, can be envisioned for the 3-D embedded capacitor in the trench of a TSV with a diameter of 50 µm and a depth of 30 µm. In addition, a finite element simulation is performed to ensure the structural integrity of the 3-D embedded capacitor and its surrounding components. The simulation result shows that the maximum thermo-mechanical stress changes only slightly from 1567.8 to 1576.8 MPa when a 3-D embedded capacitor is included. Next, prototypes of 3-D embedded capacitors are fabricated successfully with an optimized process flow design and implementation. Six types of test vehicles are included in each unit cell repeated over the entire wafer: (1) the de-embedded ALD type, (2) the embedded rough-ALD type, (3) the embedded smooth-ALD type, (4) the de-embedded sputtering type, (5) the embedded rough-sputtering type, and (6) the embedded smooth-sputtering type. Among them, the de-embedded test vehicles are just planar parallel capacitors without 3-D embedded capacitors for the purpose of benchmarking. After the fabrication, cross-sectional scanning electron microscope (SEM), transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDX) are performed on both ALD type and sputtering type test vehicles. The SEM and TEM pictures show ~100% step coverage of ~50 nm TiN and ~10 nm Al2O3 layers for ALD type test vehicles but poor step coverage of TiN layer for sputtering type test vehicles (the thickness drops from 400 nm on the top surface to 200 nm on the top part of the sidewall). The EDX line-scans across the stacked layers provide semi-quantitative proof of correct stoichiometries of TiN/Al2O3/TiN/SiO2/Si layers. Lastly, capacitance-voltage (C-V) and current-voltage (I-V) characterizations are performed to evaluate the electrical performance of the test vehicles of 3-D embedded capacitors. The C-V characterization results show that, as the trench diameter increases from 10 to 50 µm, the capacitance increases from 98.7 to 625.2 pF for ALD type 3-D embedded capacitors. It also increases from 3.6 to 138.7 pF for sputtering type 3-D embedded capacitors. As a result, the capacitance density can reach up to 3856.4 nF/mm2 for fabricated porotypes in this study. These measurement results of the ALD type test vehicles are found to be in good agreement with the corresponding electrical modelling results, which are calculated based on the analytical equations derived early in the study. However, this is not the case for the sputtering test vehicles. The difference is due to the super conformal step coverage of electrodes provided by ALD and the poor step coverage of electrodes provided by sputtering. Furthermore, the results of the other set of C-V characterizations show that the dielectric composition and the total amount of trapped charges in the dielectric layer tend to be instable when the sidewall roughness increases from 30 nm to 290 nm. From the I-V characterization results, it can be observed that the leakage currents of the ALD type embedded test vehicles do not deviate from those of their planar capacitor counterparts, but the leakage currents of the sputtering type embedded test vehicles degrade from the leakage currents of their planar capacitor counterparts. The suspected cause is the rough trench sidewall due to sputtering deposition method. Then, the I-V characterization results are normalized to the current density (J-E) plots, showing that the leakage current density is ~2×10-7 A/cm2 at 2 MV/cm and the dielectric strength is ~9.7 MV/cm for the ALD type test vehicles; whereas the leakage current density is ~3×10-9 A/cm2 at 2 MV/cm and the dielectric strength is ~8.0 MV/cm for the sputtering type test vehicles. Based on the J-E plots, leakage current conduction mechanisms have been identified for all test vehicles. The Schottky emission, FN tunneling, PF emission, and hopping conduction can be fitted for the ALD type test vehicles; whereas FN tunneling, and PF emission can be fitted for the sputtering type test vehicles. This technology is promising in integration of ultrahigh-density on-chip capacitor. The above merits will pave the way for on-chip energy storage element, integrated voltage regulator, capacitively coupled wireless module and many other possibilities.||URI:||https://hdl.handle.net/10356/102666
|DOI:||https://doi.org/10.32657/10220/48586||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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