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Title: Early output quasi-delay-insensitive array multipliers
Authors: Balasubramanian, Padmanabhan
Maskell, Douglas
Naayagi, R. T.
Mastorakis, Nikos
Keywords: Arithmetic Circuits
DRNTU::Engineering::Computer science and engineering
Issue Date: 2019
Source: Balasubramanian, P., Maskell, D., Naayagi, R. T., & Mastorakis, N. (2019). Early output quasi-delay-insensitive array multipliers. Electronics, 8(4), 444-. doi:10.3390/electronics8040444
Series/Report no.: Electronics
Abstract: Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.
ISSN: 2079-9292
DOI: 10.3390/electronics8040444
Rights: © 2019 The Authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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