Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90044
Title: A neuromorphic-hardware oriented bio-plausible online-learning spiking neural network model
Authors: Qiao, G. C.
Hu, S. G.
Wang, J. J.
Zhang, C. M.
Ning, N.
Yu, Q.
Liu, Y.
Chen, Tu Pei
Keywords: Neuromorphic Hardware
Online Learning
Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Qiao, G. C., Hu, S. G., Wang, J. J., Zhang, C. M., Chen, T. P., Ning, N., . . . Liu, Y. (2019). A neuromorphic-hardware oriented bio-plausible online-learning spiking neural network model. IEEE Access, 7, 71730-71740. doi:10.1109/ACCESS.2019.2919163
Series/Report no.: IEEE Access
Abstract: Neuromorphic hardware inspired by the brain has attracted much attention for its advanced information processing concept. However, implementing online learning in the neuromorphic chip is still challenging. In this paper, we present a bio-plausible online-learning spiking neural network (SNN) model for hardware implementation. The SNN consists of an input layer, an excitatory layer, and an inhibitory layer. To save resource cost and accelerate information processing speed during hardware implementation, online learning based on the spiking neural model is realized by trace-based spiking-timing-dependent plasticity (STDP). Neuron and synapse activities are digitalized, and decay behaviors of neuron and synapse parameters are realized by the bit-shift operation. After learning training set from the Modified National Institute of Standards and Technology (MNIST), the spiking neural model successfully recognizes the digits from the MNIST test set, showing the feasibility and capability of the model. The recognition accuracy increases significantly from 90.0% to 94.5% with the number of the excitatory/inhibitory neurons rising from 400 to 3,500, which provides a guide to make a trade-off between the recognition accuracy and the resource cost during hardware implementation. Encouragingly, compared to its corresponding floating-point model, the proposed model reduces the hardware resources and power consumption by 40.7% and 36.3%, respectively (under 55-nm CMOS process).
URI: https://hdl.handle.net/10356/90044
http://hdl.handle.net/10220/49348
DOI: http://dx.doi.org/10.1109/ACCESS.2019.2919163
Rights: Articles accepted before 12 June 2019 were published under a CC BY 3.0 or the IEEE Open Access Publishing Agreement license. Questions about copyright policies or reuse rights may be directed to the IEEE Intellectual Property Rights Office at +1-732-562-3966 or copyrights@ieee.org.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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