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Title: Efficient circuit-designs using spintronic devices
Authors: Deb, Suman
Keywords: Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2019
Source: Deb, S. (2019). Efficient circuit-designs using spintronic devices. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The last 50 years of Moore’s Law have witnessed a continuous shrinkage of CMOS technology node in the sub-micron range. While this has facilitated more and more transistors to be accommodated in the same silicon area, thereby increasing the computation power of microprocessors, smaller transistors drain more power in their OFF state. Due to increasing standby or leakage power, they cannot be downsized further. This, so called, power wall ignited the interest in non-volatile technologies like Spintronics, Phase Change Memory (PCM)and Resistive RAM (ReRAM). Spintronics, with devices like, Spin Transfer Torque (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetracks (RTs) in its arsenal, has emerged as a prospective paradigm for future logic- and storage-applications. Spintronics promise for efficient processing and storage of information lies in its attributes of non-volatility, excellent integration-density, near-unlimited endurance and compatibility with CMOS process-technology. While spin devices make excellent candidates for storage, their capability to realize logic functions remains a relatively-new and less-chartered area of research. One of the primary reasons for this is that, despite multiple optimizations at technology-, device- and circuit-level, spin-based circuits suffer from poor energy-efficiency due to the high energy consumed by write operations. In this thesis, we first aim to address this challenge. We propose design optimizations to reduce the number of write operations in Domain Wall motion-based logic circuits, and therefore, achieve overall gain in energy performance. As a case study, we perform in-depth study of the cutting-edge cryptographic block cipher SIMON, using experimentally validated Verilog-A models of MTJ and Racetrack Memory. For this benchmark, simulations demonstrate 4.65x reduction in computation energy, 2.66x improvement in computation delay and 1.71x reduction in transistor count compared to its base implementation using Racetrack Memory. Recently, a great deal of scientific endeavour has been devoted to developing spin-based neuromorphic platforms owing to the ultra-low-power benefits offered by spin devices and the inherent correspondence between spintronic phenomena and the desired neuronal, synaptic behaviour. Whereas domain wall motion-based threshold activation unit has previously been demonstrated for neuromorphic circuits, it remains well-known that neurons with threshold activation cannot completely learn non-linearly separable functions. Our research in the later half of the thesis addresses this fundamental limitation by proposing two novel domain wall motion-based dual-threshold activation units (AUs). Furthermore, new learning algorithms are formulated for neurons with these activation functions. We perform 100 trials of 10-fold training and testing of our neural networks on real-world data sets taken from the UCI machine learning repository. On an average, we observe that: 1. The learning algorithm for the first proposed-AU performs 1.08x–1.82x better than that of the perceptron learning algorithm. 2. The learning algorithm for the second AU achieves 1.04x–6.54x lower misclassification rate (MCR) than the traditional perceptron learning algorithm. In circuit-level simulation, the neural networks with the proposed activation unit are observed to outperform the perceptron networks by as much as 2.98x in MCR. The energy consumption of a neuron having the proposed domain wall motion-based activation unit averages to 35 fJ approximately. In the next step of the roadmap of this PhD work, we investigate another interesting application of a neuron with the latter AU (proposed above). As we know, a Boolean function, before being mapped to hardware, undergoes representation in terms of basic logic-primitives followed by its optimization (w.r.t. size, depth, etc.). Today’s state-of-the-art EDA tools primarily use AND-Inverter Graphs (AIGs), Majority-Inverter Graphs (MIGs) and XOR-Majority Graphs (XMGs) for representing Boolean functions. To be able to utilize the existing EDA tools for implementing spin-based logic circuits, it is important that the logic primitives in these data structures can be natively realized by spin devices. We demonstrate how the XMGs and the AIGs synthesized by EDA flows can be more-efficiently mapped to spintronic fabric using a domain wall motion-based XOR-primitive. Extensive circuit-level simulations are carried out to benchmark this XOR-gate over other domain wall motion-based gates. In addition, we develop a device-to-system simulation-framework to precisely evaluate the post-mapping (to domain wall gates) performances of synthesized networks. Our study over several challenging benchmark-suites shows that the use of this XOR-gate improves the {size, depth, size·depth, energy, EDP} performances of mapped XMGs and AIGs by average values of {31.54%, 19.00%, 41.56%, 38.03%, 45.47% and {13.39%, 9.26%, 17.74%, 15.90%, 19%}, respectively.
DOI: 10.32657/10220/49470
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Theses

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