Design and implementation of enhanced lightweight memory-based and monostable physical unclonable functions
Zhong, Hui Shu
Date of Issue2019-08-05
School of Electrical and Electronic Engineering
With the rise of internet of things, mobiles devices leveraging on the omnipresence of the wireless connectivity have grown exponentially. To enable device identification and authentication, hardware security modules are embedded into the sensor, wireless and mix-signal integrated circuits. Silicon Physical Unclonable Function (PUF) is an emerging technology to augment or substitute existing cryptographic modules for more robust and lightweight hardware security and privacy protection. Over the last decade, it has gained a strong foothold in cryptographic key generation, device identification and authentication applications. Its security rests in the intrinsic complexity and irreproducibility of a random physical disorder system instead of hard-to-solved mathematical problems. Device signature generated by PUF cannot be physically replicated even by the original manufacturer with the same photolithography masks due to the uncontrollable nature of manufacturing process variations. Even though PUFs have been well recognized today as an efficient primitive for key preservation/generation and authentication protocols, some designs have also been criticized for several drawbacks. The research in this dissertation will review these problems and propose the implementations of a higher entropy memory-based weak PUF and an enhanced diode-clamped inverter monostable strong PUF. Compare to other weak PUFs, the most important advantage of memory PUF is that it is almost cost free as the existing memory circuit in an integrated system can be reused for PUF response generation without requiring additional circuitry. The proposed dual port static random access memory (SRAM) PUF addresses two major limitations of existing SRAM PUFs. Firstly, a typical SRAM PUF needs an external memory to temporarily buffer the originally stored data before it is reset to generate the PUF response if the PUF response is needed in the midst of computations. Secondly, traditional SRAM PUF can only generate one response bit per cell. The proposed dual-port SRAM weak PUF could generate up to a maximum of four uncorrelated response bits per cell. Response bits are generated by launching two pairs of complementary data into the dual ports in write-write operation mode without resetting the entire memory array, which reduced the area-power overhead and potential security leakage caused by data transfer to buffer storage and data-remanence attacks. Post-layout simulation results based on UMC65nm CMOS model has corroborated its superior correlation, reliability, uniqueness and randomness properties. A novel monostable inverter-based strong PUF is also realized in this thesis. This proposed PUF is a new strong PUF structure featuring low power consumption and high area efficiency. The process variability of this proposed PUF can be enlarged by challenge-driven parallel inverter stage before the monostable output is amplified to a distinct binary output. The proposed enhanced lightweight monostable strong PUF harnesses the robust and reliable feedback stabilized entropy source of diode-clamped inverters (DC-INVs) in subthreshold region. Due to manufacturing process variations, the noise-immune monostable output of parallelly connected end-to-end DC-INVs is Gaussian distributed around half Vdd. The spread of the distribution is dispersed symmetrically by a challenge-driven parallel inverter stage before the output is buffered into a distinct binary state. The DC-INVs in these two stages are shared by a demultiplexer-multiplexer (DeMUX-MUX) pair in each block and the following parallel inverter buffer is also challenge-controlled to eliminate the systemic bias and improve the response uniformity. The inverter connections to the DeMUX-MUX in each block are also permuted to increase the modelling complexity against machine learning attacks. The 128-bit monostable PUF prototype chip was fabricated in 40nm CMOS technology. It consumes 14400 µm2 and 17 pJ per bit. The raw worst-case reliability is 94.1% over 40ºC to 120ºC and 0.9V to 1.3V. The average and worst-case uniformities are 50% and 54%, respectively. The prediction accuracies of support vector machine and covariance matrix adaptation – evolution strategy algorithms with more than 3000 training challenge-response pairs converge at 49% and 48.5%, respectively.
Engineering::Electrical and electronic engineering