dc.contributor.authorChong, Kwen-Siong
dc.contributor.authorGwee, Bah Hwee
dc.contributor.authorChang, Joseph Sylvester
dc.date.accessioned2009-08-03T03:54:29Z
dc.date.available2009-08-03T03:54:29Z
dc.date.copyright2007en_US
dc.date.issued2007
dc.identifier.citationChong, K. S., Gwee, B. H. & Chang, J. S. (2007). Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors. IEEE journal of solid-state circuits, 42(9), 2034-1045.en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://hdl.handle.net/10220/6004
dc.description.abstractTwo 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1–1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features 37% lower energy per FFT/IFFT computation than the sync approach but with 10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35- m CMOS process) can be operated at 1.0 V and dissipates 93 nJ.en_US
dc.format.extent12 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE journal of solid-state circuitsen_US
dc.rightsIEEE Journal of Solid-State Circuits © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleEnergy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processorsen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/JSSC.2007.903039
dc.description.versionPublished versionen_US


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