A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
Yeo, Kiat Seng
Rofail, Samir S.
Date of Issue1998
School of Electrical and Electronic Engineering
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-µm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates.
DRNTU::Engineering::Electrical and electronic engineering
IEEE journal of solid-state circuits
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