dc.contributor.authorYeo, Kiat Seng
dc.contributor.authorRofail, Samir S.
dc.identifier.citationYeo, K. S., & Samir, S. R. (1998). A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. IEEE Journal of Solid-State Circuits, 33(1), 164-168.en_US
dc.description.abstractNew BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-µm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates.en_US
dc.format.extent5 p.en_US
dc.relation.ispartofseriesIEEE journal of solid-state circuitsen_US
dc.rightsIEEE Journal of Solid-State Circuits © 1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleA charge-trapping-based technique to design low-voltage BiCMOS logic circuitsen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.versionPublished versionen_US

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