dc.contributor.authorZhu, Ning
dc.contributor.authorGoh, Wang Ling
dc.contributor.authorZhang, Weija
dc.contributor.authorYeo, Kiat Seng
dc.contributor.authorKong, Zhi Hui
dc.identifier.citationZhu, N., Goh, W. L., Zhang, W., Yeo, K. S., & Kong, Z. H. (2009). Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. pp, 1-5.en_US
dc.description.abstractIn modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.en_US
dc.format.extent5 p.en_US
dc.relation.ispartofseriesIEEE transactions on very large scale integration (VLSI) systemsen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleDesign of low-power high-speed truncation-error-tolerant adder and its application in digital signal processingen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.versionPublished versionen_US

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