Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/93106
Title: IP watermarking using incremental technology mapping at logic synthesis level
Authors: Cui, Aijiao
Chang, Chip Hong
Tahar, Sofiène
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Cui, A., Chang, C. H., & Tahar, S. (2008). IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(9), 1565-1570.
Series/Report no.: IEEE transactions on computer-aided design of integrated circuits and systems
Abstract: This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead.
URI: https://hdl.handle.net/10356/93106
http://hdl.handle.net/10220/6259
ISSN: 0278-0070
DOI: 10.1109/TCAD.2008.927732
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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