Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/92285
Title: Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
Authors: Yu, Hao
Shi, Yiyu
He, Lei
Karnik, Tanay
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2008
Source: Yu, H., Shi, Y., He, L., & Karnik, T. (2008). Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(12), 1609-1619.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126x faster to obtain temperature, and reduces the number of thermal vias by 2.04x under the same temperature bound.
URI: https://hdl.handle.net/10356/92285
http://hdl.handle.net/10220/6262
ISSN: 1063-8210
DOI: http://dx.doi.org/10.1109/TVLSI.2008.2001297
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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