Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/92314
Title: A study of on-chip stacked multi-loop spiral inductors
Authors: Zhang, Yue Ping
Yang, Kai
Yin, Wen Yan
Shi, Jinglin
Kang, Kai
Mao, Jun Fa
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Yang, K., Yin, W. Y., Shi, J., Kang, K., Mao, J. F., & Zhang, Y. P. (2008). Study of On-Chip Stacked Multiloop Spiral Inductors. IEEE Transactions on Electron Devices. 55(11), 3236-3245.
Series/Report no.: IEEE transactions on electron devices
Abstract: This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.
URI: https://hdl.handle.net/10356/92314
http://hdl.handle.net/10220/6264
ISSN: 0018-9383
DOI: http://dx.doi.org/10.1109/TED.2008.2004648
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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