Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91706
Title: An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
Authors: Jaya, Gibran Limi
Chan, Pak Kwong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Source: Jaya, G. L., & Chan, P. K. (2009). An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power. In proceedings of the 12th International Symposium on Integrated Circuits: Singapore, (pp.433-436).
Abstract: A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the op-amp for reducing power driving requirement. The amplifier is designed using CSM 1.8V 0.18μm triple-well CMOS process technology and simulated using realistic BSIM3 models. The amplifier dissipates only 15.14μW at a dual power supply of ±0.9V. It has has a gain of 40dB at dc and 38.5dB at 3.2kHz. The estimated passband inputreferred noise is 2.08μVrms.
URI: https://hdl.handle.net/10356/91706
http://hdl.handle.net/10220/6340
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Appears in Collections:EEE Conference Papers

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