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|Title:||A provably passive and cost-efficient model for inductive interconnects||Authors:||Yu, Hao
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2005||Source:||Yu, H., & He, L. (2005). A provably passive and cost-efficient model for inductive interconnects. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 24(8), 1283-1294.||Series/Report no.:||IEEE transactions on computer aided design of integrated circuits and systems||Abstract:||To reduce the model complexity for inductive interconnects, the vector potential equivalent circuit (VPEC) model was introduced recently and a localized VPEC model was developed based on geometry integration. In this paper, the authors show that the localized VPEC model is not accurate for interconnects with nontrivial sizes. They derive an accurate VPEC model by inverting the inductance matrix under the partial element equivalent circuit (PEEC) model and prove that the effective resistance matrix under the resulting full VPEC model is passive and strictly diagonal dominant. This diagonal dominance enables truncating small-valued off-diagonal elements to obtain a sparsified VPEC model named truncated VPEC (tVPEC) model with guaranteed passivity. To avoid inverting the entire inductance matrix, the authors further present another sparsified VPEC model with preserved passivity, the windowed VPEC (wVPEC) model, based on inverting a number of inductance submatrices. Both full and sparsified VPEC models are SPICE compatible. Experiments show that the full VPEC model is as accurate as the full PEEC model but consumes less simulation time than the full PEEC model does. Moreover, the sparsified VPEC model is orders of magnitude (1000 ) faster and produces a waveform with small errors (3%) compared to the full PEEC model, and wVPEC uses less (up to 90 ) model building time yet is more accurate compared to the tVPEC model.||URI:||https://hdl.handle.net/10356/90614
|ISSN:||0278-0070||DOI:||http://dx.doi.org/10.1109/TCAD.2005.850820||Rights:||© 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Journal Articles|
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