Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/93564
Title: An enhanced low-power high-speed adder for error-tolerant application
Authors: Zhu, Ning
Goh, Wang Ling
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2009
Source: Zhu, N., Goh, W. L., & Yeo, K. S. (2009). An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th International Symposium on Integrated Circuits, (pp.69-72) Singapore.
Abstract: The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test—Error- Tolerance (ET), we managed to develop a novel Error-Tolerant Adder which we named the Type II (ETAII). The circuit to some extent is able to ease the strict restriction on accuracy to achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETAII is able to achieve more than 60% improvement in the Power- Delay Product (PDP). The proposed ETAII is an enhancement of our earlier design, the ETAI, which has problem adding small number inputs.
URI: https://hdl.handle.net/10356/93564
http://hdl.handle.net/10220/6350
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