dc.contributor.authorMeher, Manas Ranjan
dc.contributor.authorJong, Ching Chuen
dc.contributor.authorChang, Chip Hong
dc.date.accessioned2010-08-25T04:08:02Z
dc.date.available2010-08-25T04:08:02Z
dc.date.copyright2008en_US
dc.date.issued2008
dc.identifier.citationMeher, M. R., Jong, C. C., & Chang, C. H. (2008). High-speed and low-power serial accumulator for serial/parallel multiplier. IEEE Asia Pacific Conference on Circuits and Systems, pp.176-179, Macau, China.
dc.identifier.urihttp://hdl.handle.net/10220/6353
dc.description.abstractThis paper presents a new approach to serial/parallel multiplier design by using parallel 1's counters to accumulate the binary partial product bits. The 1's in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results in a very small carry save adder (CSA) array or tree required before the two final summands are added up to obtain the final product. The counters can be clocked at very high frequency (around 1.5 GHz as dictated mainly by the TFF propagation delay) and the accumulation frequency is independent of the operand size. The proposed accumulation method achieves 33%, 38%, 43% gain in speed respectively for 31, 63, 127 operands accumulators and on average 42% reduction in power consumption over CSA based accumulation implemented in 0.18 µm CMOS technology.en_US
dc.format.extent4 p.en_US
dc.language.isoenen_US
dc.rights© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
dc.titleHigh-speed and low-power serial accumulator for serial/parallel multiplieren_US
dc.typeConference Paper
dc.contributor.conferenceIEEE Asia Pacific Conference on Circuits and Systems (2008 : Macau)en_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/APCCAS.2008.4745989
dc.description.versionPublished versionen_US


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